FRAM™ (Ferroelectric Random Access Memory) has achieved the non-volatility of stored data (for example, retaining performance for about ten years), and the excellent characteristics of the high speed data write-in performance for about several 10 ns for example, by using the hysteresis characteristic which a ferroelectric capacitor has.
On the other hand, since it is necessary to drive comparatively large capacitor for control of the hysteresis characteristic of the ferroelectric capacitor, it is difficult to achieve a high-speed operation of an SRAM (Static Random Access Memory) level, which has the access time for about several ns for example, in the present condition. Moreover, since the characteristics of the ferroelectric capacitor deteriorated gradually whenever it repeated polarization inversion, there was a problem that a number of times of data rewriting is limited to about 1014 times per one capacitor.
In order to solve this problem, there is a method of using a ferroelectric capacitor as a mere capacitive element at the time of normal operation, executing a DRAM (Dynamic Random Access Memory) mode operation for holding data with quantity of electrical charges charged up, and executing an FRAM mode operation for applying data into non-volatilizing using the hysteresis characteristic only at the time of power supply cutoff (for example, refer to Patent Literature 1 and Patent Literature 2).
In this method, since improvement in the speed of operation can be achieved by not using the hysteresis characteristic at the time of normal operation, but reducing the capacitor to drive, and polarization inversion is not occurred, it is effective in the ability to suppress the characteristic degradation of a device.
In the DRAM mode, it becomes advantageous to high-speed operation so that the capacitor of the BL (Bit Line) to which a memory cell is connected is small, but by one side, in the FRAM mode, in order to read residual polarization electrical charges, great BL capacitor is needed. Since the BL capacitor can be applied small by this trade-off only in the range in which the FRAM mode can operate, improvement in the speed has a limit.
When holding data also in a power OFF period, it is necessary to execute data write-in with the FRAM mode for the memory cell, which is operating in the DRAM mode, and to apply the data into non-volatilizing, at the time of power supply cutoff. For this reason, the operating time in the FRAM mode needed at the time of power supply cutoff becomes long as memory space becomes large.
Furthermore, there is a problem that a data transfer rate deteriorates since it cannot be treated as well as SRAM and is incompatible by restrictions that access is impossible from external during the refresh cycle (refresh penalty).
Although a refresh penalty is reducible to some extent if a method to divide and compose a memory into a plurality of banks, and to refresh except the bank for an external access request is used, the refresh penalty occurs since the external access is refused when a certain specific bank A is refreshed, when the access request occurs concentrating on the specific bank A.
As a method to solve this problem, a technology of concealing a refresh cycle completely by preparing a cache memory for the inside of a memory, and executing refresh operation when a cache hits for the access request from the outside (a memory cell array is not accessed) is proposed (for example, refer to Patent Literature 3). In Patent Literature 3, a read-out/write-in buffer for preventing from being affected by the influence of refresh of semiconductor memory, and an operation method for the same, are disclosed.